The present invention relates generally to the field of integrated circuit manufacturing, and more specifically, to depositing and removing sacrificial material from voids or openings in a dielectric layer on a semiconductor substrate.
Sacrificial material has been used in integrated circuit manufacturing to fill voids or openings in a dielectric layer on a semiconductor substrate. For example, sacrificial material has been used in processes for providing dual damascene metal interconnects in integrated circuits. Sacrificial material allows the lithography and etching process to effectively apply to a substantially hole-free surface, similar to a surface without voids or openings.
One type of sacrificial material is sacrificial light absorbing material (SLAM), which includes or is associated with a light absorbing material or dye so that it acts as an anti-reflective coating during the lithography process. By dyeing the sacrificial material, changes in substrate reflectivity may be reduced, enabling the photolithographic process to produce improved results.
Sacrificial material generally has been a spin-on-polymer (SOP) or spin-on-glass (SOG) deposited by spin coating to fill openings in the dielectric layer. For example, sacrificial material may consist of a solution of low molecular weight organosilicate polymer and small molecule additives such as reaction catalysts, surfactant and co-solvent, and an organic chromophore or dye to absorb incident light and minimize reflection.
The dual damascene concept involves forming both a via and a trench in the dielectric layer or interlayer dielectric (ILD). For example, the via may be etched first. Sacrificial material may be spin-coated onto a patterned substrate, i.e., a wafer with vias patterned into an exposed dielectric material. After spin-coating, the sacrificial material should fill the vias completely and provide a defect-free planar surface on the wafer, and leave between about 500 and 3,000 angstroms of the material on the surface of the device.
After filling the vias, the sacrificial material may be baked to crosslink the polymer network, forming a carbon-containing silicate glass having a dry etch rate similar to the dielectric. A photoresist then may be coated over the substrate, and a trench may be etched, removing sacrificial material at about the same rate as the dielectric layer.
After the trench is etched, residual photoresist may be removed by ashing. During ashing, carbon in the sacrificial material is oxidized, breaking off the polymer network and evolving as waste gases such as carbon dioxide, water, etc. As a result, sacrificial material may change from a carbon-containing silicate glass to a weakened low carbon-silicate glass. Any remaining sacrificial material may be removed by a combination of plasma processing and wet chemistry steps. The via and trench then are filled with a conductive material such as copper to form a conductive layer of interconnects.
Sacrificial material has several properties including anti-reflection, dry etch rate, planarization and cleaning properties. However, these properties have not been controlled except through changes to the organosilicate polymer and, to a limited extent, the casting solvent and additives such as surfactant. However, optimizing one property, such as gap-fill, may be sub-optimal for other properties, such as the dry etch rate. Properties of the sacrificial material have not been optimized independently. Additionally, some organic dyestuffs used for light-absorption may not be phase compatible with organosilicate or other matrix materials and can present additional difficulties such as migration into adjacent photoresist layers.
There is a need to optimize properties of sacrificial material independently. There is a need for sacrificial material with improved gap-fill properties without increasing the dry etch rate or adversely affecting other properties, especially on substrates having significant topography. There is a need for an improved sacrificial material to fill voids or openings in a dielectric layer in dual damascene or similar processes in semiconductor manufacturing, especially in sub 0.25 micron structures.